Location:Home > Engineering science > Control Theory and Engineering > Research on Design and Realization of the IP-Core Based Morse Processing System on a Chip

Research on Design and Realization of the IP-Core Based Morse Processing System on a Chip

Downloads: []
Tutor: LiRenFa WangShuLiang
School: Hunan University
Course: Control Theory and Engineering
Keywords: SOC,Microcontroller,IP core,IP soft-core,MORSE code,VHDL,FPGA
CLC: TN402
Type: Master's thesis
Year:  2005
Facebook Google+ Email Gmail Evernote LinkedIn Twitter Addthis

not access Image Error Other errors

IP soft-core and FPGA SOC chip design to solve the long development cycle of the ASIC chip design , high cost, high risk and product time to market sensitivity , the SOC design more flexible , fast , based IP soft-core and FPGA SOC design technology rapidly developed and applied in the consumer electronics, automotive electronics , industrial design . Therefore , it has become the industry's hot spots . This paper analyzes the IP soft core and FPGA the SOC technology theory and some typical application platform based on the basis of technical methods mc8051Core IP soft-core and FPGA - based design and build a the MORSE code processing SOC system architecture , design and implementation a deal with Morse code serial asynchronous Receiver Transmitter ( M - SART the Morse - serial asynchronous receiver / Transmitter ) function module IP core . In this paper , from Mores electrical characteristics of the code symbol start , comparative analysis of the Morse code and ASCII code serial asynchronous transmission characteristics of the signal frame difference , a Morse codes digitized , on this basis , the provisions of a MORSE code serial The asynchronous frame transmission protocol. Analyzing the function from Core8051 - IP core structure and design hierarchy to complete the design of the nuclear structure and design of the Morse signal processing system hierarchy . And comparative analysis , using a hardware description language VHDL to achieve a the MORSE code Serial Asynchronous Receiver Transmitter ( M - SART ) module IP soft-core design . By means of EDA tools MaxPlus II integrated development environment complete the M - SART module IP core debugging FPGA - oriented layout and logic synthesis , and the M - the SART module IP soft-core FPGA timing simulation and experimental results show that , M- SART processing the results of the MORSE code is correct and reliable operation , the operating frequency of the M - SART 34.12MHz , fully able to match Core8051 IP core operating frequency .
Related Dissertations
Last updated
Sponsored Links
Home |About Us| Contact Us| Feedback| Privacy | copyright | Back to top