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Design of the Hardware-in-the-loop Simulation System in Phased-array Doppler Log

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Tutor: ZhangDianLun
School: Harbin Engineering University
Course: Underwater Acoustics
Keywords: hardware-in-the-loop simulation,Doppler log,DDS,DSP,phased-array
CLC: TP391.9
Type: Master's thesis
Year:  2012
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The phased-array Doppler Velocity log(PADVL), as a kind of instrument supplyingprecision velocity and the theoretical basis of it is Doppler effect, it is not only highmeasurement precision, and does not require the speed of sound compensation, In recentyears it has been widely used at home and abroad. Compared with other log, although thePhased-array Doppler Log, there are many advantages, however, but their functional tests andaccuracy tests are often more difficult, traditionally, marine trial and pool trial usually. Inorder to save the cost of trial, shorten the development cycle of the instrument, need to designa set of test equipment, Tested the instrument in the terrestrial environment, to determine theperformance and status.The paper discusses the design and development of the hardware-in-the-loop SimulationSystem in Phased-Array Doppler Log, it has the characteristics of the low cost and portability.Firstly, the article introduces the systems development background, on this basis, according tothe requirements of the phased-array Doppler Log, design the hardware and softwareimplementations of the hardware-in-the-loop Simulation System in Phased-Array DopplerLog, author design the circuit of signal processing and generating using TI¡¯sTMS320VC5509A DSP and ADI¡¯s DDS chip AD9959, to achieve real-time simulation of theecho signal. Finally, after the online debugging trial, the results show that the system isworking well; the indicators of the system can meet the requirements of the phased-arrayDoppler Log.
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