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Design of Multi-Channel Receiver and Data Acquisition System for Multi-beam Echo Sounder

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Tutor: LiHaiSen
School: Harbin Engineering University
Course: Underwater Acoustics
Keywords: Multi-channel,Receiver,Data acquisition,FPGA,Multi-beam echosounder
CLC: TP274.2
Type: Master's thesis
Year:  2012
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Multi-beam Echo Sounder is a seafloor landform detecting device with high-efficiency,high-accuracy and high-resolution as well, which is widely used in the fields such asunderwater topography observation, marine resources exploration, continental margin survey,channel survey, underwater search, underwater building observation, marine environmentalmonitoring and so on. In the background of Multi-beam Echo Sounder system project,multi-channel receiver, multi-channel data acquisition circuit and FPGA logic are designedbased and debugged on scheme research of the three parts.In this paper, the single-channel receiver circuit is made into a signal receiving module,which is connected to the motherboard with the pins to form a whole receiver. In the processof designing the signal receiving module of the multi-channel receiving, the characteristics ofthe noise of noise sources and integrated op-amp are studied, and on this basis, controllablegain amplifier circuit, band-pass filter circuit and fixed gain amplifier circuit are designed. Aneight-order infinite gain multiple feedback band-pass filter is used as the filter circuit of thereceiver. The filter parameters are determined by theoretical calculations and Multisimsoftware simulations. Consistency between channels is considered as a key to meet the systemdesign requirements.FPGA is used as main controller in the multi-channel data acquisition circuit. The ADCcircuit, gain control circuit and data transmission interface circuit are also designed in thispart. In the process of designing ADC circuit, paper demonstrates over-sampling ADC schemeand uses Delta-Sigma ADC to make the analog-digital conversion to the receiver outputanalog signals.FPGA control logic for each functional module is designed using Verilog HDL hardwaredescription language in the software environment of Quartus II, including ADC controlmodule, data processing module and HOTLink control module, and the function and timingfor each module is verified by simulation.
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