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The Research of the Passive Sonar Signal Detection and the Design Based on DSP

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Tutor: QiuHongAn
School: Northwestern Polytechnical University
Course: Underwater Acoustics
Keywords: Passive sonar,Line spectrum detection,DSP,CPLD,USB
CLC: U666.7
Type: Master's thesis
Year:  2007
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With the rapid development of science and technology, the sonar equipment gradually to the development of digital, intelligent. Signal detection as one important task of the sonar signal processing, its performance will directly affect the entire system, and therefore developed a high-performance signal processing system it is necessary to detect. Passive sonar to detect the target in accordance with the noise of the radiation emitted by the target navigation and discriminant target type, line spectrum of passive sonar detection line is to ship radiated noise spectral components extracted from the broadband background noise, in order to achieve sonar correct detection of the target. Departure from the view of engineering, conducted a preliminary study on passive sonar signal detection theory and algorithms, and then focuses on the real-time implementation of DSP algorithm. Firstly from the theory discussed passive sonar detection research status, to achieve significance, and its basic theory. On this basis, the line spectrum detection based on adaptive line Enhancer Chirp-Z transform combined detection algorithm, a simulation study in Matlab. Then discuss the functional tasks of signal processing system, and algorithms for the calculation amount is estimated and the real-time analysis. On this basis, mainly to high-performance DSP core, the DSP DRAM CPLD combination of signal processing system hardware technology programs. Using the modular design concept, the completion of each module block diagram design. Then focus on each module specific hardware circuit design, circuit schematic and PCB diagram drawn in Protel. The main design of the circuit including the DSP clock, power, reset and watchdog circuit, external expansion Flash, JTAG interface, a dual-port RAM, the McBSP multi-machine communication, asynchronous communication, the USB2.0 interface circuit, the CPLD logic circuit, drive circuit. In the the Quartus ¢ò completed the CPLD logic control circuit design. Hardware design based on the various functions in this system software design, hardware and software algorithms for the preparation of the program, including the detection algorithm subroutine, management control procedures, FLASH programming procedures, serial communication program, the user interface programming, USB firmware, drivers, and so on. Finally, the system control panel, for example, to debug the hardware circuits and software algorithms, debugging problems, make the system function to the basic realization.
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