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Design and Development of the Panoramic Camera Hardeare System

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Tutor: ZuoGuoFeng
School: Northeastern University
Course: Control Theory and Control Engineering
Keywords: Panorama,TMS320DM642,VHDL,Color space conversion,I~2C controller,Multi-way cache
CLC: TN948.41
Type: Master's thesis
Year:  2009
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Abstract:
Panoramic camera system can get 360¡ãomni-directional image/video information and a high-photorealistic panorama virtual realization can be formed after processing images with software. The panoramic camera system can be used in widespread scopes, such as panoramic monitoring, environment detection, intelligent robot, and digital city.etc. It is a new area with a valuable research in theory and practical aspect.The hardware system of panoramic camera is mainly about images information collection and preprocession. At present, most of panoramic cameras or devices are realized by images information gathering with special cameras lens or turning one camera around, but it is rare to see the device which can get panoramic high-resolution images simultaneously. According to these deficiencies, hardware system which meets the hardware requirements of panoramic camera system is proposed based on a comprehensive view of domestic and foreign developments in panoramic acquisition system in this thesis. The main contributions of this dissertation are listed as follows.1. Analysis the advantages and disadvantages of current hardware system, and propose the design requirement and requirement analysis for the hardware system. The development work of panoramic camera hardware system is completed.2. In order to obtain high-resolution images, the industrial camera is selected as an important acquisition part, on which secondary development can be done. Acquisition part is an industrial camera array collection. A new scheme of panoramic controller based on DSP+ FPGA is proposed, which can finish the function of collecting, integrating, preprocessing and storing of the large real-time data.3. The data integration module is designed based on FPGA with VHDL hardware description language, which includes the functions as follows:triggering multi-channel camera at the same time, real-time data caching, implementing format conversion of the image data from RGB to YCrCb color space and so on. 4. The data compression module based on TMS320DM642 is designed. As for hardware part, SDRAM extended circuit, system power circuit and related FPGA and DSP communication peripheral circuits are designed. As for software part, the system software is compiled and debugged, and joint debugging of overall functions is achieved.
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