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Research of Processor Performance Optimization Based on Function Dynamic Reuse

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Tutor: FuZhongChuan
School: Harbin Institute of Technology
Course: Computer Science and Technology
Keywords: Superscalar Processor,SimpleScalar,Function dynamic reuse
CLC: TP332
Type: Master's thesis
Year:  2008
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The performance of modern computer systems is measured in terms of the number of instructions per cycle (IPC). Modern architectures rely on instruction-level parallelism to improve performance. In order to get taller IPC, processor executes multiple instructions every cycle, often executes instructions in an order other than that specified by the program. In order to increase the number of instructions that can be issued, speculative excution is often employed by statically in VLIW or dynamically in superscalar systems. Numerous techniques exist to predict conditional instructions in an attempt to insert instructions into the execution pipeline as early as possible and minimize the pipeline stalls. Similar to branch prediction, value prediction and address predictions have received considerable interest in recent years. It should be noted that the underlying theme in all these techniques is the ability of the architectures to execute instructions in a speculative mode, and quashing the result when the speculation fails. While all speculative techniques increase IPC counts, it should be noted that the effective execution time of an application is not reduced and in some cases it is increased to account for the time needed to undue an incorrect speculation.Speculative technique do increase IPC, but do not necessarily increase the number of useful instructions executed. Continuing this trend, most recently, researchers are exploring reuse technology, and it has aroused great concern. In this paper we want to extend the scope of reuse to function level. Reuse technology is non-speculative technology, to reduce the implement of redundant instruction by invoking previous executed result. Reuse technology can be devided into three kinds through granularity sizes, include: instruction reuse, basic block reuse and trace reuse. Continuing this trend, in this paper we explored coarser granularity function reuse technology.The basic principle of technology of function dynamic reuse is: abstract the function feature dynamicly accmpanied with the implementation of process, and store the information of function feature in the function reuse table. When the function is recalled, search the function reuse table. If the feature is a match with the feature produced by implement of prior function, invoke the result of the former function to avoid redundant execution of the function, then renew the status of the processor and cntinue to execute the next instruction. If there is no match when the search ends, execute the function, and store the read set and the write set into the function reuse table when finished implement of the function and woule get ready for the coming call.Technology of function dynamic reuse operates with function. It is implemented by reducing the execued numbers of instructions, even not to execute redundancy function and invoke prior result of function. Function reuse is a coarse-granularity-level reuse technology. Applying the technology into the design of architecture can elevate the efficiency of the processor, to enhance the performance of processor and to lower the power consumption.
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